1. Field of the Invention
The embodiments generally relate to integrated circuit chips incorporated into electronic assemblies, such as flip-chip assemblies and stacked chip assemblies, using controlled collapsed chip connections (i.e., C4 connections). More particularly, the embodiments relate to an integrated circuit chip and a method of forming the chip with pyramid or cone-shaped conductive input/output (I/O) pads.
2. Description of the Related Art
As discussed in detail in U.S. Patent Application Publication No. 2009/0146316 of Jadhav et al., filed on Dec. 5, 2007, published on Jun. 11, 2009, assigned to International Business Machines Corporation of Armonk, N.Y., and incorporated herein by reference, in a flip-chip assembly an integrated circuit chip is typically mounted on a chip carrier by an array of controlled collapsed chip connections (i.e., C4 connections). The formation of such C4 connections usually involves the formation of solder balls on flat conductive pads on the active surface of an integrated circuit chip (e.g., on the same surface of the chip as the integrated circuit devices and, preferably, surrounding a core integrated circuit device region), thereby creating an array of solder bumps. Additionally, solder paste is deposited onto conductive pads within an array of openings (e.g., solder resist openings) on the surface of a chip carrier. The array of solder bumps on the integrated chip is aligned with the array of solder paste filled openings on the chip carrier. Next, the integrated circuit chip and chip carrier are pressed together and a reflow process is performed to create the solder joints (i.e., the C4 connections) that both electrically and mechanically connect the integrated circuit chip to the chip carrier. Similar C4 connections can be used to interconnect integrated circuit chips in a stacked chip assembly.
Unfortunately, during chip operation, stress-related cracks in the C4 connections and/or the integrated circuit chip(s) can form due to a mismatch in thermal expansion (e.g., between the integrated circuit chip and the chip carrier in a flip-chip assembly and between the multiple integrated circuit chips in a stacked chip assembly). Such stress-related cracks can result in chip failure. Furthermore, such stress-related cracks can increase exponentially with the use of an organic laminate substrate as the chip carrier in a flip-chip assembly, with the use of lead-free solder material and/or with smaller pitch C4 connections (i.e., with greater C4 connection density). Therefore, there is a need in the art for an improved C4 connection that will provide greater flexibility and, thereby improved integrated circuit chip reliability.